System for providing interrupts in a numerical control system

ABSTRACT

A system for reliably applying interrupts to a numerical control system is described. The computer which processes the control data of the Numerical Control System periodically checks to see if an interrupt from an external device is present. The inventive system constrains the interrupts to the least significant pulse positions of the device addresses. The presence of interrupt pulses at the more significant pulse positions results in the automatic disabling of an interrupt system. The reliability of the system is therefore greatly enhanced because illegal or erroneous interrupts do not disturb the normal functioning of the system.

United States Patent [1 1 Henegar SYSTEM FOR PROVIDING [NTERRUFIS IN ANUMERICAL CONTROL SYSTEM [451 Aug. 28, 1973 Primary Examiner-Gareth D.Shaw Attorney-Lester L. Hallacher et al.

[75] inventor: Hubert B. Henegar, Detroit, Mich. [73] Assignee: TheBendix Corporation, Southfield, 57] ABSTRACT Mich.

. A system for reliably applying interrupts to a numerical [22] Flled'1972 control system is described. The computer which pro- [2l] Appl.No.: 249,446 cesses the control data of the Numerical Control Systemperiodically checks to see if an interrupt from an external device ispresent. The inventive system con- IZIZ] $5.8]. 34041715 strains theimermpts to the least significant pulse p 'Fi 9/18 tions of the deviceaddresses. The presence of interrupt I 1 le 0 arc i pulses t the e g ntpulse positions results in the automatic disabling of an interruptsystem. The reli- [56] References Cited ability of the system istherefore greatly enhanced be- UNITED STATES PATENTS cause illegal orerroneous interrupts do not disturb the 3,553,656 1/1971 Bernhardt340/|72.5 normal functioning of the system. 3,370,276 2/l968 Schell Jr.340/l72.5 3,538,504 n/mo Higginbotham 340/1725 6 Claims 1 'fi 8" s IAll/0 AND I 5 6 26 T 5/ .i: i a? fl/YO m 6 a CROSS REFERENCES TO RELATEDAPPLICATIONS The invention described herein is an improvement of thesystem described in application Ser. No. 62,244 filed Aug. 6, I970 by H.B. Henegar and Robert .1. Patterson and said application is useful inunderstanding the environment in which the instant invention isemployed.

The invention described herein can be employed in a system including theinvention described in application Ser. No. 249,447 entitled NumericalControl System Control Program Loader" filed of even date here with byH. B. Henegar and assigned to the assignee of the instant application.The invention described herein can be employed in a system also includedin the invention described in application Ser. No. 249,448 entitledOutput Command Decoder for Numerical Control Equipment" filed of evendate herewith by H. B. Hencgar and assigned to the assignee of theinstant application.

The invention described herein can also be employed with the inventiondescribed in application Ser. No. 249,445 entitled "Control System forPlural Tape Readers in an N/C System" filed of even date herewith by H.B. Henegar and assigned to the assignee of the instant application.

BACKGROUND OF THE INVENTION Many numerical control systems employ acomputer to process the data which effects the control of servo motors,pulse motors or the deflection coils of a CRT so that an element such asa cutting tool, graphic pen, or electron beam can be controlled in twoor three dimensional space in accordance with the data processed by thecomputer. Because a computer processes all the data which controls theexternal devices employed in the numerically controlled machine, itfrequently becomes necessary to inform the computer that there is asignal available from an external device so that some operation can beperformed on this external device. The signal which informs the computerthat an external device is to be energized is ordinarily called aninterrupt and hence, the term interrupt is defined in the numericalcontrol art as a signal which is used to interrupt the ordinaryfunctioning of the computer so that the function or operation requiredof the interrupting device can be performed. Only a single interruptsignal line exists and any device that wishes to interrupt places asignal on this line. After the completion of the performance of theinterrupting device, the computer returns to its ordinary routine at theplace where it left off before the interrupt was received.

In existing numerical control equipment, either one of the two possibletechniques are ordinarily employed to detect the source of an interruptsignal into the computer. In the first system, the external devicegenerates the interrupt signal which interrupts the ordinary functioningof the computer as soon as the computer completes the operation definedby the current instruction. Upon command by the computer (a specificpulse is output), the interrupting device supplies its interrupt addressto the computer.

In another technique the computer sequentially scans or scrutinizes theexternal devices to determine whether or not, if any, which externaldevice or devices has generated an interrupt signal. if such a signal isdetected, the computer proceeds to perform the interrupting operation onthe external device and returns to the programmed routine at the end ofthe interrupting operation. These techniques are well known to thoseskilled in the art and are employed in various manners in most allnumerical control equipment.

SUMMARY The inventive system is primarily intended for usage in thefirst type of system wherein the interrupting external device suppliesan address to the computers when commanded to do so by the computer.Thus, in the inventive system if an external device provides aninterrupt signal, the computer detects the source of the interruptsignal and then performs the desired operation on the external device.Each interrupting device has a particular address by which the computercan identify the external device. As is known, an address is composed ofa series of logic ONE's and ZEROs and each particular arrangement ofONE's and ZERO's forms a different address. Accordingly, in a computercapable of inputting an eight bit address from the inter ruptingexternal device, 256 distinct addresses are available.

However, all 256 addresses are rarely used for 256 external devices andhence the interrupt address often is confined to the least significantpulse positions of the external device address, and the more significantpulse positions are always ZERO. Accordingly, if an interrupt address isbeing input to the computer, the logic ONE's will appear only on theaddress digits having the lesser significance while the digits of moresignificance will be logic ZERO. If a logic ONE occurs on one of themore significant digits, the inventive interrupt system automaticallyforces all digits to logic ZERO causing the device address of ZERO to beinput to the computer. The computer then shuts down since it has beenprogrammed to recognize a ZERO address as an error condition. The numberof pulse positions which must be allowed to go to logic ONE is dependentupon the number of interrupts which are to be employed. Thus, if threeinterrupts are to be employed in the system, either or both of the leastsignificant two digits can be logic ONE. Alternatively, seven interruptscan be accommodated by permitting any combination of the three leastsignificant digits to be logic ONEs and fifteen interrupts can beaccommodated utilizing the four least significant digits, etc. If, say,only six interrupting devices exist in the system and they haveinterrupt addresses l-6, the inventive circuitry would not prevent theinsertion of device address 7 but would block addresses greater than 7.In order to sense the error condition that exists when an address of 7is entered into the computer, software means must be provided. The meansof doing this is well known, and would be employed to insure thereliability of the system.

The inventive system is therefore advantageous because the presence of alogic ONE on any of the more significant digit results in an orderly andcontrolled shutdown of the system so that erroneous interrupts do notcause malfunctioning of the entire numerical control system. In theabsence of this scheme, a considerable amount of computer program andprogram storage is typically required to sense the presence ofnonsensical device addresses and to provide the orderly shutdown.

BRIEF DESCRIPTION OF THE DRAWINGS The FIGURE shows a preferredembodiment of the inventive system.

DETAILED DESCRIPTION OF THE DRAWINGS The FIGURE shows a plurality ofinterrupt device (ID) signals, identified as ID through ID07, beingapplied to the inventive interrupt system over Input Leads II through 18respectively. Because eight ID signals are available, as many as 256different combinations of ZERO's and ONEs can be applied to Input Leadsll through 18. Accordingly, as many as 256 external devices can haveindividual addresses represented by the ID signals. However, dependingupon the number of external devices which must be capable of providinginterrupt signals to the computer, only a limited number of InputSignals (ID) need be allowed to become logic ONE when inputting theinterrupting devices addresses to the computer. For example, as shown inthe FIGURE, only the ID00 and [D01 signals can be used to identify threeinterrupt addresses. If either or both of ID00 or IBM become logic ONE,a logic ONE is available on either output Line 32 or 33 and is thereforeinput to the computer. Thus, the ID00 and [D01 signals are permitted tobecome logic ONE to indicate the address of a legitimate interrupt.However, as explained hereinafter if any one of the ID03 to ID07 signalsbecome logic ONE, the system automatically shuts down.

It should be understood that by using only the ID00 and lDOl signals togenerate interrupts, three external devices can interrupt the computer.If ID02 also is permitted to generate an interrupt as many as seveninterrupt signals can be generated and as many as seven external deviceswill be capable of interrupting the computer.

AND Gates 21 through 28 are two input AND gates and each of the ANDgates receives an ID input and an input from OR Gate 29 by way of Lead31. The Output Leads 34 to 39 of AND Gates 23 to 28 are connected to ORGate 41 by way of Lines 49 to 54, respectively. The output of OR Gate 41is applied to one input tenninal of a dual input AND Gate 42. The outputof AND Gate 42 is coupled to one input terminal of an OR Gate 43. Theoutput of OR Gate 43 is coupled by way of an Inverter 55 and Lead 44 toone input terminal of OR Gate 29 and the output of OR Gate 29 isconnected to the other input terminal of OR Gate 43 by way of anInverter 56 and Line 46. OR Gate 29 also enables AND Gates 2] to 28 overLead 31. AND Gate 42 also receives an Input-Output Acknowledge (IOAK)signal by way of Lead 47. [OAK is a signal output by the computer whenan interrupt occurs which commands the interrupting device to send itsaddress to the computer. OR Gate 29 also receives an interrupt SystemEnable (ISE) signal on Input Terminal 48.

In operation, when a logic ONE signal is available on either or both ofOutput Leads 32 and 33 of AND Gates 21 and 22 and not on Leads 34-39while IOAK is a logic ONE, a permissible device address is being input.This address is received and the computer proceeds to carry out thefunction dictated by the interrupting device. Because of theavailability of two logic ONE signals on Output Leads 32 and 33, threediffercm addresses, [-3, can be utilized. The fourth possible address,0, can not be assigned to a device as will become clear later. If it isdesired to permit more than three devices to provide the interrupt,Output Lead 34 will also be allowed to go to logic ONE without disablingthe system This will be accomplished by eliminating Line 49 whichcouples output Terminal 34 to the input of OR Gate 41. In similarmanner, if it is desired to permit between 7 to 15 external devices tointerrupt the computer, Lead 50 which couples Output Terminal 35 of ANDGate 24 to OR Gate 41 will be eliminated. It should also be appreciatedthat if desired, the address can contain more, or less, than eightdigits so that the number of ID signals applied to the system can beincreased or decreased accordingly.

Because the presence of logic ONEs on Output Leads 32 and 33 areintended to be the only perrnissible device addresses, the presence oflogic ONEs on Output Leads 34 through 39 of AND Gates 23 through 28while the [OAK signal is present must be effective in shutting down theentire interrupt system. This is accomplished by the preferredembodiment of the inventive system shown in the FIGURE in the followingmanner:

Firstly, the system is enabled by the application of a logic ONEInterrupt System Enable Pulse (ISE) to Input Terminal 48 of OR Gate 29.Once applied, the logic ONE output from OR Gate 29 is passedsequentially through Inverter 56, OR Gate 43, Inverter 55 and then backto the second input terminal of OR Gate 29. The ISE signal may thenreturn to logic ZERO while all other signals in the above chain of logicwill remain unchanged. With a logic ONE signal present at the output ofOR Gate 29 on Lead 31. AND Gates 2] through 28 all are enabled such thattheir outputs will equal their corresponding ID inputs. These outputsconnect directly to the computer and are the means by which the addressis input to the computer.

Because of the logic table of an AND Gate, the application of theinput-Output Acknowledge signal (IOAK) to Input Terminal 47 conditionsAND Gate 42, to yield a logic ONE only when the output of OR Gate 41 isa logic ONE. If the output of OR Gate 41 goes to logic ONE, AND Gate 42simultaneously receives two high, or logic ONE, inputs and as known tothose skilled in the art, the AND Gate then generates a logic ONEoutput. The output of AND Gate 42 is directed to OR Gate 43. The outputof OR Gate 43 becomes logic ONE and the second input to OR Gate 29becomes logic ZERO because of the Inverter 55. The continued operationof the system requires a logic ONE output from OR Gate 29 because thesignal applied to OR Gate 29 over Input Terminal 48 was removed afterthe system was actuated. Accordingly, anytime the AND Gate 42 outputgoes to ONE, the output of OR Gate 29 goes to ZERO removing the enablingsignal from Line 31 so that AND Gates 21 through 28 are immediatelydisabled. Hence, any ONEs which had appeared on Leads 32 through 39 areremoved and an effective device address of ZERO is input to thecomputer. The computer is programmed to treat an interrupt from anapparent device ZERO as an error condition and will cause an orderly andsafe shutdown of the numerical control system when such a conditionoccurs.

Hence, in the initial operation of the system, the application of theInterrupt System Enable pulse (ISE) enables each of AND Gates 21 through28. Logic ONE's appearing on the ID inputs to these gates are passedthrough to the computer as long as the ID02 through lD07 inputs remainat a low state while the lOAK signal is a logic ONE. Accordingly, bothinputs to AND Gate 42 are not at logic ONE simultaneously. Because ANDGate 42 receives a logic ZERO input from OR Gate 41 and a logic ONEinput from the [OAK signal or vice-versa, its output remains a logicZERO and therefore OR Gate 43 yields a ZERO output which is changed tologic ONE by lnverter 55. OR Gate 29 then enables AND Gates 21 through28. However, if any of the lD02 through 1007 signals goes high to logicONE while lOAK is a ONE, the output terminal of the AND gate whichreceives the high lD signal goes high and causes OR Gate 41 to yield alogic ONE output. This logic ONE is applied to AND Gate 42 causing ANDGate 42 to generate a logic ONE output. When a logic ONE output isapplied to OR Gate 43, a logic ZERO is applied to OR Gate 29 so that itsoutput goes low, thereby disabling AND Gates 2] through 28.

After the system is disabled in the manner described hereinabove, thelSE interrupt enable signal must be applied to OR Gate 29 over InputLead 48 and after this signal is applied for a very short period oftime, it can be removed because the system is self-sustaining by theoperation of feedback loop including Inverters 55 and 56 and OR Gates 43and 29.

I claim:

I. in a system for controlling a plurality of external devices with adata storage device wherein each of said external devices has a uniqueaddress represented by a string of logic pulses having sequentiallylesser address significance and each pulse being either of two logiclevels, an interrupt system for enabling said external devices toindividually apply interrupting address signals to said data storagedevice, said interrupting address signals being present when a selectednumber of said address pulses in the lower significance positions are ata selected one of said two logic states, said interrupt systemincluding:

first means for receiving said interrupting address signals and anenable signal and producing at least one interrupt signal and at leastone response signal;

second means for receiving all of said at least one response signals andgenerating said enable signal when all of said at least one responsesignals are at one logic level and a disable signal when any of said atleast one response signals is at another logic level so that said firstmeans produces no output signals when said disable signal is generatedby said second means.

2. the system of claim 1 wherein said first means for receiving includesa plurality of logic means individually responsive to said interruptingdevice address signals and said enable signal, a portion of said logicmeans producing said interrupt when said device interrupting addresssignals and said enable signals are of the same logic state, and theremainder of said logic means producing said response signals when saidenable signal and all of said device address interrupting signals aredifferent.

3. the system of claim 2 wherein said second means for receivingincludes gate means for receiving said response signals and producingsaid enable signal when all of said response signals are at a logicstate different from the logic state of said interrupt address signalsand said disable signal when any one of said response signals has alogic state the same as the state of said inte rrupt address signals.

4. in a numerical control system for controlling external devices withdata from a computer. a system for transmitting device address interruptsignals from an external device to said computer, wherein a plurality ofaddress pulses indicative of the address of an external device isavailable to said computer in parallel form and said device addressinterrupt signals are represented by one logic state of said addresspulses, said system for transmitting device address interrupt signalscomprising:

a plurality of logic means equal in number to said plurality of addresspulses for individually and simultaneously receiving said pulses;

system enable logic means for receiving a system start signal andproducing an enable signal, each of said plurality of logic meansreceiving said enable signal and producing a signal of one logic statewhen said address pulse and said enable signal are the same as said onelogic state, and a signal of another logic state for all othercombinations of logic states of said address pulses and said enablesignal;

enable signal retention means responsive to a first portion of saidplurality of logic means for actuating said system enable logic meanswhen said first portion of said plurality of logic means all yield anoutput different from said one logic state and for disabling said firstportion of logic means for other combination of said address pulses andsaid outputs, the remainder of said plurality of logic means alsoreceiving said enable signal to produce said interrupt signals when saidenable signal and said address pulses are the same logic state, saidremainder of said logic means receiving the address pulses of the lessersignificance.

5. The system of claim 4 wherein said address pulses are applied to saidremainder of said logic means at a first logic state, and said enablesignal is at said first logic state so that said interrupt pulses areproduced at said first logic state, and said address pulses are appliedto said first portion of said logic means at a second logic state;

and wherein said enable signal retention means includes gate means forproducing said enable signal at said first logic state when all of saidaddress pulses applied to said first portion of said logic means are atsaid second logic state, and said enable signal retention means disablessaid system for transmitting interrupt signals when any one of saidaddress pulses to said first portion of said logic means becomes saidfirst state.

6. The system of claim 4 wherein said enable signal retention meansincludes first gate means responsive to said first portion of saidplurality of logic means and producing an output of said one logic statewhen said address pulses and said enable signal are said one logicstate, and producing an output of said other logic state;

and logic means for receiving and inverting the output of said firstgate means to thereby provide said enable signal when said addresspulses and said enable signal are different.

t I t l 4

1. IN A SYSTEM FOR CONTROLLING A PLURALITY OF EXTERNAL DEVICES WITH ADATA STORAGE DEVICE WHEREIN EACH OF SAID EXTERNAL DEVICES HAS A UNIQUEADDRESS REPRESENTED BY A STRING OF LOGIC PULSES HAVING SEQUENTIALLYLESSER ADDRESS SIGNIFICANCE AND EACH PULSE BEING EITHER OF TWO LOGICLEVELS, AN INTERRUPT SYSTEM FOR ENABLING SAID EXTERNAL DEVICES TOINDIVIDUALLY APPLY INTERRUPTING ADDRESS SIGNALS TO SAID DATA STORAGEDEVICE, SAID INTERRUPTING ADDRESS SIGNALS BEING PRESENT WHEN A SELECTEDNUMBER OF SAID ADDRESS PULSES IN THE LOWER SIGNIFICANCE POSITIONS ARE ATA SELECTED ONE OF SAID TWO LOGIC STATES, SAID INTERRUPT SYSTEMINCLUDING: FIRST MEANS FOR RECEIVING SAID INTERRUPTING ADDRESS SIGNALSAND AN ENABLE SIGNAL AND PRODUCING AT LEAST ONE INTERRUPT SIGNAL AND ATLEAST ONE RESPONSE SIGNAL; SECOND MEANS FOR RECEIVING ALL OF SAID ATLEAST ONE RESPONSE SIGNALS AND GENERATING SAID ENABLE SIGNAL WHEN ALL OFSAID AT LEAST ONE RESPONSE SIGNALS ARE AT ONE LOGIC LEVEL AND A DISABLESIGNAL WHEN ANY OF SAID AT LEAST ONE RESPONSE SIGNALS IS AT ANOTHERLOGIC LEVEL SO THAT SAID FIRST MEANS PRODUCES NO OUTPUT SIGNALS WHENSAID DISABLE SIGNAL IS GENERATED BY SAID SECOND MEANS.
 2. the system ofclaim 1 wherein said first means for receiving includes a plurality oflogic means individually responsive to said interrupting device addresssignals and said enable signal, a portion of said logic means producingsaid interrupt when said device interrupting address signals and saidenable signals are of the same logic state, and the remainder of saidlogic means producing said response signals when said enable signal andall of said device address interrupting signals are different.
 3. thesystem of claim 2 wherein said second means for receiving includes gatemeans for receiving said response signals and producing said enablesignal when all of said response signals are at a logic state differentfrom the logic state of said interrupt address signals and said disablesignal when any one of said response signals has a logic state the sameas the state of said interrupt address signals.
 4. In a numericalcontrol system for controlling external devices with data from acomputer, a system for transmitting device address interrupt signalsfrom an external device to said computer, wherein a plurality of addresspulses indicative of the address of an external device is available tosaid computer in parallel form and said device address interrupt signalsare represented by one logic state of said address pulses, said systemfor transmitting device address interrupt signals comprising: aplurality of logic means equal in number to said plurality of addresspulses for individually and simultaneously receiving said pulses; systemenable logic means for receiving a system start signal and producing anenable signal, each of said plurality of logic means receiving saidenable signal and producing a signal of one logic state when saidaddress pulse and said enable signal are the same as said one logicstate, and a signal of another logic state for all other combinations oflogic states of said address pulses and said enable signal; enablesignal retention means responsive to a first portion of said pluralityof logic means for actuating said system enable logic means when saidfirst portion of said plurality of logic means all yield an outputdifferent from said one logic state and for disabling said first portionof logic means for other combination of said address pulses and saidoutputs, the remainder of said plurality of logic means also receivingsaid enable signal to produce said interrupt signals when said enablesignal and said aDdress pulses are the same logic state, said remainderof said logic means receiving the address pulses of the lessersignificance.
 5. The system of claim 4 wherein said address pulses areapplied to said remainder of said logic means at a first logic state,and said enable signal is at said first logic state so that saidinterrupt pulses are produced at said first logic state, and saidaddress pulses are applied to said first portion of said logic means ata second logic state; and wherein said enable signal retention meansincludes gate means for producing said enable signal at said first logicstate when all of said address pulses applied to said first portion ofsaid logic means are at said second logic state, and said enable signalretention means disables said system for transmitting interrupt signalswhen any one of said address pulses to said first portion of said logicmeans becomes said first state.
 6. The system of claim 4 wherein saidenable signal retention means includes first gate means responsive tosaid first portion of said plurality of logic means and producing anoutput of said one logic state when said address pulses and said enablesignal are said one logic state, and producing an output of said otherlogic state; and logic means for receiving and inverting the output ofsaid first gate means to thereby provide said enable signal when saidaddress pulses and said enable signal are different.